This invention relates to preparing semiconductor die for electrical interconnection in a stacked die assembly; and to die so prepared and die assemblies containing die so prepared.
Interconnection of die with one another in a stack of die (“die-to-die”; “z-interconnection”) or of a die or a die stack with a substrate (“die-to-substrate”) presents a number of challenges. For example, the integrated circuitry is situated on an “active side” of the die, and exposed pads are situated on the active side of the die for electrical interconnection with other die or with a substrate. When die are stacked, one die in the stack may obscure the pads on another die, making them inaccessible for interconnection, particularly where die having the same or similar dimensions are stacked one over another.
Some die as provided have die pads along one or more of the die margins, and these may be referred to as peripheral pad die. Other die as provided have die pads arranged in one or two rows near the center of the die, and these may be referred to as center pad die. The die may be “rerouted” to provide a suitable arrangement of interconnect pads at or near one or more of the edges of the die.
A die edge along which interconnect pads are arranged may be referred to as an “interconnect edge”; the margin of the die on the active side adjacent the interconnect edge may be referred to as an “interconnect margin”, and the sidewall of the die adjacent the interconnect edge may be referred t as an “interconnect sidewall”.
Various kinds of die interconnection have been proposed, including among others flip-chip interconnect, wire bond interconnect, and tab bond interconnect.
Where wire bond interconnect is employed in a stacked die assembly, the wire bonds may be formed to connect pads on the active side of a first die before an additional die is stacked over it. A spacer is typically provided upon the active side of the first die, to prevent interference by the second die with the wire loops on the first die.
Approaches to z-interconnection of die, other than by wire bonds, bumps, or tabs are described, for example, in U.S. Pat. No. 5,675,180 and its progeny; and, for example, in U.S. Pat. No. 7,215,018 and, for example, in U.S. Pat. No. 7,245,021.
Particularly, for example, U.S. Pat. No. 7,245,021 describes “off-die” interconnection, employing interconnection terminals electrically connected to peripheral sites on the die and projecting beyond the die edge; z-interconnection of the die is made by electrically conductive polymer elements into which the projecting parts of the interconnection terminals extend.
It can be advantageous to carry out certain processing steps at the wafer level, prior to singulation of the die. At some stage in die preparation, the wafer is cut to singulate the die. That is, the wafer is cut (for example, by sawing the wafer along “streets” between active circuit regions of the die), forming an array of die (a “wafer array”) on the wafer support. The singulated die can then be manipulated individually (for example by use of a “pick-and-place” tool) for further treatment.
U.S. application Ser. No. 12/124,077, referenced above, describes various die stack configurations, including, among others, offset die stacks, and staggered die stacks, and including stacks in which the various die in the stack have various dimensions.
U.S. application Ser. No. 12/142,589, referenced above, describes methods for passivation (forming electrical insulation) onto die surfaces at the wafer or wafer array level.
U.S. application Ser. No. 12/323,288, referenced above, describes methods for separating die from a wafer by cutting the wafer in two stages. The first wafer cutting procedure includes cutting along a first set of saw streets to a depth greater than the prescribed die thickness and optionally along a second set of saw streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along a second set of streets. Subsequent to the first cutting procedure, and prior to the second cutting procedure, additional die preparation procedures that are sensitive to die shift may be carried out. In some such methods the first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other such methods the wafer is thinned to the prescribed die thickness prior to carrying out the first wafer cutting procedure. In some examples of the method the first cut is made along saw streets fronting interconnect edges.
The patents and patent applications referenced herein above and below are incorporated by reference herein.